Analog digital converter

ABSTRACT

In one aspect, provided is an A/D converter including: a plurality of capacitor networks each including a first switch group; a capacitor group; a second switch group; and a plurality of reference voltage selectors; a sampling unit grounded at one end thereof; a plurality of A/D converters; and converting means; and a plurality of switch networks each of which connects a corresponding one of the plurality of the capacitor networks to any one of the sampling unit and the plurality of A/D converters in one-to-one correspondence, and in which converter the switch networks change the connections between the plurality of capacitor networks, the sampling unit and the plurality of A/D converters, at each predetermined time intervals, so that a pipeline operation is performed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of application Ser. No. 12/019,020filed on Jan. 24, 2008, which is based upon and claims the benefit ofpriority from the prior Japanese Patent Application No. 2007-14866,filed Jan. 25, 2007, the entire contents of both of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an analog-to-digital converter forconverting an analog signal into a digital signal.

2. Description of the Related Art

As analog-to-digital converters (hereinafter, referred to as “A/Dconverters”) converting analog signals into digital signals, a pipelineA/D converter has been known, which performs an analog to digitalconversion (hereinafter, referred to as an “A/D conversion”) in eachstage while sending signals in pipeline to subsequent stages (see, forexample, Japanese Patent Laid-Open No. 2004-214905)

Further, a cyclic A/D converter which is configurable with a smallernumber of devices than the pipeline A/D converter has also been known(see, for example, Japanese Patent No. 3046005)

As disclosed in, for example, Japanese Patent Laid-Open No. 2004-214905,in these A/D converters, after the analog signals are sampled and heldin a sample-and-hold circuit, the A/D conversion is performed byrepeating conversion stages.

In each conversion stage, a residual signal calculated in the previousstage is used to calculate an A/D conversion result of the residualsignal, and also a new residual signal. Then, the A/D conversion resultis sent to a digital synthesis circuit, while the new residual signal issent to the next stage. The calculation of a residual signal is calledan MDAC (Multiplying Digital to Analogue Conversion) calculation.

As disclosed in, for example, FIG. 3 of Japanese Patent Laid-Open No.2004-214905, each conversion stage includes a sub-A/D converter, and anMDAC circuit. The MDAC circuit calculates the residual signal.

The MDAC circuit in FIG. 3 of Japanese Patent Laid-Open No. 2004-214905is, specifically, configured by a circuit having a capacitor asdisclosed in FIG. 5 of Japanese Patent Laid-Open No. 2004-214905. In acircuit disclosed in FIG. 5 of Japanese Patent Laid-Open No.2004-214905, after the residual signal calculated in a previous stage issampled and held in a capacitor as a charge, an MDAC calculation isperformed.

Here, in order to increase the accuracy of the A/D conversion, it isnecessary to increase the accuracy of calculation of an A/D conversionresult and a residual signal in each conversion stage. Since both theA/D conversion result and the residual signal are calculated by using aresidual signal calculated in the previous conversion stage, it isnecessary to cause a sample-and-hold accuracy of the residual signalcalculated in the previous conversion stage to converge to a certainrange.

That is, in order to increase the accuracy of the A/D conversion, asettling time for the sample-and-hold accuracy of the residual signal toconverge to a certain range is necessary. This requires some convergencetime.

As means to correct an error in A/D conversion on each conversion stage,an A/D converter which corrects an error in digital bit data obtainedthrough an A/D conversion has been also provided (see, for example,Japanese Patent Laid-Open No. 2003-174364).

In this A/D converter, an A/D conversion result is an output in binarycode having 1.5 bits of information and has 0.5 bits of redundancy.Since the A/D converter has the redundancy, the accuracy requirement ofan A/D conversion part is relaxed compared with that of an A/D converterhaving no redundancy.

However, even using this method, the problem still remains that samplingis still necessary to output a residual signal to a subsequent stage,and a certain amount of settling time is required.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the present invention, provided is an A/Dconverter including: a first switch group configured to be connected toan input terminal into which an analog signal is inputted; a capacitorgroup configured to be connected to the first switch group, and to storetherein the analog signal inputted from the input terminal as a charge;a second switch group configured to be connected to the capacitor group,and the second switch configured to transfer the charge in the capacitorgroup; a operational amplifier configured to be connected to thecapacitor group and the second switch group, the operational amplifierconfigured to subtract a predetermined voltage from a voltage generatedin the capacitor group in conjunction with the transfer of the charge,and the operational amplifier then configured to set, as an outputvoltage, a voltage obtained by amplifying the result of the subtraction;converter configured to be connected to the operational amplifier, andthe converter configured to convert the output voltage into a digitalvalue of a predetermined number of bits, including a redundancy bit; anda plurality of reference voltage selectors configured to be connected tothe first switch group and the capacitor group, and each of whichselects the predetermined voltage in accordance with the digital value,and in which the connecting of the capacitor group to the operationalamplifier, and the voltage selection of each reference voltage selector,are performed for a plurality of times.

Further, according to another aspect of the present invention, providedis also an A/D converter including: a plurality of capacitor networkseach including a first switch group configured to be connected to aninput terminal into which an analog signal is inputted; a capacitorgroup configured to be connected to the first switch group, and thecapacitor group configured to store the analog signal inputted from theinput terminal as a charge; a second switch group configured to beconnected to the capacitor group, and the second switch group configuredto transfer the charge in the capacitor group; and a plurality ofreference voltage selectors configured to be connected to the firstswitch group and the capacitor group, and each of which selects apredetermined voltage in accordance with the digital value; a samplingunit grounded at one end thereof; a plurality of A/D converters eachincluding a operational amplifier configured to subtract thepredetermined voltage from a voltage generated in the capacitor group inconjunction with the transfer of the charge, and the plurality of A/Dconverters configured to then sets, as an output voltage, a voltageobtained by amplifying the result of the subtraction; and converterconfigured to be connected to the operational amplifier, and theconverter configured to convert the output voltage into a digital valueof a predetermined number of bits, including a redundancy bit; and aplurality of switch networks each of which connects a corresponding oneof the plurality of the capacitor networks to any one of the samplingunit and the plurality of A/D converters in one-to-one correspondence,and in which converter the switch networks change the connectionsbetween the plurality of capacitor networks, the sampling unit and theplurality of A/D converters, at each predetermined time intervals, sothat a pipeline operation is performed.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a cyclic A/D converter of a firstembodiment.

FIG. 2 is a view showing A/D conversion operation by a sub-A/Dconverter.

FIG. 3 is a view showing digital encoding by a digital encoding circuit.

FIG. 4 is a flowchart showing the order of A/D conversion of the A/Dconverter of FIG. 1.

FIG. 5 is a view showing an equivalent circuit at first sample and holdtime in the A/D converter of FIG. 1.

FIG. 6 is a view showing the equivalent circuit at first MDACcalculation time in the A/D converter of FIG. 1.

FIG. 7 is a view showing the equivalent circuit at second MDACcalculation time in the A/D converter of FIG. 1.

FIG. 8 is a view showing the equivalent circuit at third MDACcalculation time in the A/D converter of FIG. 1.

FIG. 9 is a block diagram showing an A/D converter of a secondembodiment.

FIG. 10A is a view showing an analog signal, and an input state into acapacitor network; and FIG. 10B is a view showing a connection statebetween a capacitor network and a sampling unit SP or A/D converters.

DETAILED DESCRIPTION OF THE INVENTION First Embodiment

An A/D converter of a first embodiment of the present invention will bedescribed with reference to the accompanying drawings.

First, a configuration and connections of the first embodiment will bedescribed with reference to FIG. 1. Next, referring to FIG. 2, anoperation of a sub-A/D converter 6 will be described. In the operation,the sub-A/D converter 6 A/D converts an output voltage of theoperational amplifier 5 into a digital value in binary code.Subsequently, referring to FIG. 3, digital encoding method in thedigital encoding circuit 15 will be described. Next, referring to FIGS.4 to 8, operation procedures will be described. In the operationprocedures, reference voltage selectors 2 to 4 select predeterminedvoltages in accordance with a digital value in binary code converted bythe sub-A/D converter 6, and an analog signal Vin inputted from anexternal input terminal 1 is A/D converted.

Configuration of First Embodiment

First, a configuration and connections of the first embodiment will bedescribed with reference to FIG. 1. FIG. 1 is a circuit diagram showinga cyclic A/D converter of the first embodiment.

As shown in FIG. 1, the A/D converter of this embodiment includes theexternal input terminal 1, reference voltage selectors 2 to 4, acapacitor group 7, a first switch group 8, a second switch group 9, theoperational amplifier 5, a switch 20, the sub-A/D converter 6, and thedigital encoding circuit 15.

The external input terminal 1 is a terminal to which an analog signalVin is inputted.

When an absolute value of a reference voltage in the A/D converter ofthis embodiment is denoted as Vref, the reference voltage selectors 2 to4 are circuits each selecting one of the following there voltages, apositive reference voltage +Vref, 0 volt, and a negative referencevoltage −Vref, in accordance with a digital value in binary code, having1.5 bits of information, converted by the sub-A/D converter 6. Thereference voltage selector 2 includes switches 23 to 25, the referencevoltage selector 3 includes switches 28 to 30, and the reference voltageselector 4 includes switches 33 to 35.

Further, digital values in binary code converted by sub-A/D converter 6are supplied to the reference voltage selectors 2 to 4 through thedigital encoding circuit 15. Referring to FIGS. 4 to 8, operation willbe described. In the operation, the reference voltage selectors 2 to 4select predetermined voltages according to the above digital value inbinary code.

The operational amplifier 5 is an op-amp of three-terminal structurehaving an input terminal (−), an input terminal (+), and an outputterminal. The switch 20 is connected between the input terminal (−) andthe input terminal (+). The input terminal (+) is grounded. The sub-A/Dconverter 6 is connected to the output terminal.

The sub-A/D converter 6 is an A/D converter having 0.5 bits ofredundancy, and is a circuit converting a voltage held and outputted bythe operational amplifier 5 into a digital value in binary code having1.5 bits of information. The digital value in binary code is supplied tothe digital encoding circuit 15. Referring to FIG. 2, an operation willbe described. In the operation, the sub-A/D converter 6 converts aninput into a digital value in binary code.

The digital encoding circuit 15 is a circuit performing an errorcorrection by adding digital values converted by the sub-A/D converter6, and performing 5-bit digital encoding. Further, the digital encodingcircuit 15 supplies digital values in binary code supplied from thesub-A/D converter 6, to the reference voltage selectors 2 to 4.

The capacitor group 7 is a group of capacitors storing an analog signalVin inputted from the external input terminal 1 as a charge andperforming an MDAC calculation. Further, the capacitor group 7 includesa first capacitor 10, a second capacitor 11, a third capacitor 12, and afourth capacitor 13.

The first capacitor 10 and the second capacitor 11 have the samecapacitance C. The third capacitor 12 has a capacitance 2C double thecapacitance of the first capacitor 10. The fourth capacitor 13 has acapacitor 4C four times the capacitance of the first capacitor 10.

The first switch group 8 is a group of switches which are closed whenstoring an analog signal Vin inputted from the external input switch 1in the capacitor group 7 as a charge, and includes a switch 21, a switch26, a switch 31, and a switch 36.

The second switch group 9 is a group of switches which are used whenperforming an MDAC calculation by switching a connection of a capacitorin the capacitor group 7, and includes a switch 22, a switch 27, aswitch 32, and a switch 37.

Connection Relationships of First Embodiment

Next, connection relationships of respective devices will be described.

A common connection is established between one end of the switch 21 andone end of the switch 22, and this common connection point is connectedto one end of the first capacitor 10. The switch 21 performs an ON/OFFoperation between the external input terminal 1 and the one end of thefirst capacitor 10. The switch 22 performs an ON/OFF operation betweenthe one end of the first capacitor 10 and the output terminal of theoperational amplifier 5. The remaining end of the first capacitor 10 isconnected to the input terminal (−) of the operational amplifier 5.

A common connection is established between one ends of the switches 23to 27, and this common connection point is connected to one end of thesecond capacitor 11. The switch 23 performs an ON/OFF operation betweenthe positive reference voltage +Vref and the one end of the secondcapacitor 11. The switch 24 performs an ON/OFF operation between 0 [V]and the one end of the second capacitor 11. The switch 25 performs anON/OFF operation between the negative reference voltage −Vref and theone end of the second capacitor 11. The switch 26 performs an ON/OFFoperation between the external input terminal 1 and the one end of thesecond capacitor 11. The switch 27 performs an ON/OFF operation betweenthe one end of the second capacitor 11 and the output terminal of theoperational amplifier 5. The remaining end of the second capacitor 11 isconnected to the input terminal (−) of the operational amplifier 5.

A common connection is established between one ends of the switches 28to 32, and this common connection point is connected to one end of thethird capacitor 12. The switch 28 performs an ON/OFF operation betweenthe positive reference voltage +Vref and the one end of the thirdcapacitor 12. The switch 29 performs an ON/OFF operation between 0 [V]and the one end of the third capacitor 12. The switch 30 performs anON/OFF operation between the negative reference voltage −Vref and theone end of the third capacitor 12. The switch 31 performs an ON/OFFoperation between the external input terminal 1 and the one end of thethird capacitor 12. The switch 32 performs an ON/OFF operation betweenthe one end of the third capacitor 12 and the output terminal of theoperational amplifier 5. The remaining end of the third capacitor 12 isconnected to the input terminal (−) of the operational amplifier 5.

A common connection is established between one ends of the switches 33to 37, and this common connection point is connected to one end of thefourth capacitor 13. The switch 33 performs an ON/OFF operation betweenthe positive reference voltage +Vref and the one end of the fourthcapacitor 13. The switch 34 performs an ON/OFF operation between 0 [V]and the one end of the fourth capacitor 13. The switch 35 performs anON/OFF operation between the negative reference voltage −Vref and theone end of the fourth capacitor 13. The switch 36 performs an ON/OFFoperation between the external input terminal 1 and the one end of thefourth capacitor 13. The switch 37 performs an ON/OFF operation betweenthe one end of the fourth capacitor 13 and the output terminal of theoperational amplifier 5. The remaining end of the fourth capacitor 13 isconnected to the input terminal (−) of the operational amplifier 5.

MDAC Calculation Operation

Next, referring to FIG. 2, operation will be described. In theoperation, the sub-A/D converter 6 converts an output voltage Vouti ofthe operational amplifier 5 into a digital value in binary code having1.5 bit of information. Here, i is a value representing the number oftimes A/D conversions are made by the sub-A/D converter. In thisembodiment, i represents 1, 2, 3 or 4. That is, Vouti takes four valuesfrom Vout1 to Vout4.

FIG. 2 is a view showing A/D conversion operation by sub-A/D converter6. According to the principle of an A/D conversion shown in FIG. 2, avoltage Vouti inputted in sub-A/D converter 6 is converted into adigital value in binary code having 1.5 bit of information, according tothe voltage range of the Vouti as follows.

-   -   [1] Case where Vouti is not greater than −Vref/4        -   The digital value in binary code is 00.    -   [2] Case where Vouti is between −Vref/4 and ₊Vref/4        -   The digital value in binary code is 01.    -   [3] Case where Vouti is not less than +Vref/4        -   The digital value in binary code is 10.

Subsequently, the MDAC calculation will be described. Vouti+1 iscalculated based on Vouti using the MDAC calculation as follows.

Vouti+1=2×Vouti−Di·Vref   (1)

-   -   (Di=−1, 0, 1) (i=1,2,3)        Here, Di is a digital value used in the MDAC calculation. Since        Vouti is a value up to Vout4, Di takes three values from D1 to        D3. This Di follows the principle of the A/D conversion shown in        FIG. 2, and is set to the following values according to Vouti.    -   [1] Case where Vouti is not greater than −Vref/4        -   Di=−1    -   [2] Case where Vouti is between −Vref/4 and +Vref/4        -   Di=0    -   [3] Case where Vouti is not less than +Vref/4        -   Di=+1

Digital Encoding Operation

Next, referring to FIG. 3, a method will be described. In the method,the digital encoding circuit 15 performs 5-bit digital encoding using adigital value in binary code converted by the sub-A/D converter 6.

FIG. 3 is a view showing a digital encoding method in the digitalencoding circuit 15. As shown in FIG. 3, the digital encoding circuit 15overlaps and adds digital values in binary code converted from the firsttime to the fourth time by the sub-A/D converter 6, so that 5-bitdigital encoding is performed.

The overlap above represents a calculation such as an addition of an LSBof a first digital value and an MSB of a second digital value, or anaddition of an LSB of the second digital value and an MSB of a thirddigital value.

When using this MDAC calculation and the digital encoding method shownin FIG. 3, an accurate digital value of a 5-bit conversion result can beobtained when the conversion error made by the sub-A/D converter 6 isless than ±Vref/4.

A/D Conversion Operation

Next, referring to FIGS. 5 to 8 based on FIG. 4, an operation procedurewill be described. In the operation procedure, the reference voltageselectors 2 to 4 select predetermined voltages according to digitalvalues in binary code converted by the sub-A/D converter 6, and ananalog signal Vin inputted from the external input terminal 1 is A/Dconverted.

FIG. 4 is a flowchart showing a calculation order of an A/D conversionmade by the A/D converter of FIG. 1. FIG. 5 is a view showing anequivalent circuit at first sample and hold time in the A/D converter ofthis embodiment. FIG. 6 is a view showing the equivalent circuit atfirst MDAC calculation time in the A/D converter of this embodiment.FIG. 7 is a view showing the equivalent circuit at second MDACcalculation time in the A/D converter of this embodiment. FIG. 8 is aview showing the equivalent circuit at third MDAC calculation time inthe A/D converter of this embodiment.

First, in the circuit shown in FIG. 1, all the switches are OFF. Next,the switches 20, 21, 26, 31, and 36 are turned on (Step S1). An analogsignal Vin is sampled in the first capacitor 10 to the fourth capacitor13. That is, the analog signal Vin is held, as a charge, in the firstcapacitor 10 to the fourth capacitor 13.

At this time, when denoting a sum of charges held in the first capacitor10 to the fourth capacitor 13 as Q, a composite capacitance of the firstcapacitor 10 to the fourth capacitor 13 becomes 8C, so that Q isexpressed by the following equation.

Q=8C·Vin   (2)

After a certain period of time has elapsed, the switches 20, 21, 26, 31,and 36 are turned off. Thereafter, Q is held in the first capacitor 10to the fourth capacitor 13.

Subsequently, the switches 22, 27, 32, and 37 are turned on (Step S2).In this case, the circuit of FIG. 1 becomes equivalent to the one shownin FIG. 5.

In the circuit of FIG. 5, the output terminal and the input terminal (−)of the operational amplifier 5 are connected through a capacitor, and anegative feedback is achieved. At this time, this circuit operates sothat a difference between voltages inputted in the input terminal (+)and the input terminal (−) becomes zero. Therefore, since the inputterminal (+) is grounded, the input terminal (−) is equivalentlygrounded.

Since the input terminal (−) of the operational amplifier 5 isequivalently grounded, the first output voltage Vout1 of the operationalamplifier 5 is outputted according to the charge held in the firstcapacitor 10 to the fourth capacitor 13.

At this time, the charge held in the first capacitor 10 to the fourthcapacitor 13 is Q shown in Equation (2), and the composite capacitanceof the first capacitor 10 to the fourth capacitor 13 becomes 8C, so thatVout1 is expressed by the following equation.

Vout1=Q/8C=Vin   (3)

At this time, the sample and hold function for the analog signal isterminated. Thereafter, the process moves to Step S3.

Next, the sub-A/D converter 6 performs a first A/D conversion accordingto the principle of the A/D conversion shown in FIG. 2 (Step S3). Thatis, Vout1 is converted to a first digital value in binary code so that avalue of D1 is determined. The first digital value is thereafter sent tothe digital encoding circuit 15. The switches 22, 27, 32, and 37 arethen turned off.

Next, the first MDAC calculation is performed as follows (Step S4).

According to the value of D1, one of the switches 33, 34 and 35 isselected. At this time, when D1=1, the switch 33 is selected; when D1=0,the switch 34 is selected; and when D1=−1, the switch 35 is selected.

Next, one selected from the switches 33 to 35, and the switches 22, 27and 32 are turned on. In this case, the circuit of FIG. 1 becomesequivalent to the one shown in FIG. 6.

At this time, a charge held in the fourth capacitor 13 is denoted by Q1,and a charge held in the first capacitor 10 to the third capacitor 12 isdenoted by Q2. The composite capacitance of the first capacitor 10 tothe third capacitor 12 becomes 4C.

The circuit shown in FIG. 6 is the one in which a negative feedback isachieved as in the circuit shown in FIG. 5, and the input terminal (−)of the operational amplifier 5 is equivalently grounded.

Since the input terminal (−) of the operational amplifier 5 isequivalently grounded, a voltage held in the first capacitor 10 to thethird capacitor 12 is outputted as an output voltage of the operationalamplifier 5. This output voltage is a result of the MDAC calculation.This output voltage Vout2 is obtained using Q2 as follows.

Vout2=Q2/4c   (4)

Next, according to the law of conservation of charge, the sum of Q1 andQ2 becomes equal to the charge Q which is firstly sampled.

Q=Q1+Q2   (5)

According to Equation (5), Q2 is expressed using the following equation.

Q2=Q−Q1   (6)

Next, a voltage to be applied to fourth capacitor 13 becomes D1*Vref.Accordingly, Q1 is expressed using the following equation.

Q1=4C·D1·Vref   (7)

Using Equations (2), (5), (6) and (7) above, Q2 becomes the followingvalue.

Q2=8C·Vin−4C·D1·Vref   (8)

Using Equations (4) and (8), Vout2 is given as follows.

Vout2=2Vin−D1·Vref   (9)

-   -   (D1=−1 or 0 or 1)        This Vout2 is a first MDAC calculation result.

Next, sub-A/D converter 6 performs a second A/D conversion according tothe principle of the A/D conversion shown in FIG. 2 (Step S5). That is,Vout2 is converted into a second digital value in binary code so that D2is determined. Subsequently, the second digital value is sent to thedigital encoding circuit 15. Next, one selected from the switches 33 to35, and the switches 22, 27 and 32 are turned off.

Next, a second MDAC calculation is performed as follows (Step S6).

One of the switches 33 to 35 is selected according to the value of D1.

One of the switches 28 to 30 is selected according to the value of D2.At this time, when D2=1, the switch 28 is selected; when D2=0, theswitch 29 is selected; and when D2=−1, the switch 30 is selected.

Subsequently, one selected from the switches 33 to 35, one selected fromthe switches 28 to 30, and the switches 22, 27 are turned on. In thiscase, the circuit of FIG. 1 becomes equivalent to one shown in FIG. 7.

At this time, a charge held in the fourth capacitor 13 is denoted as Q3;a charge held in the third capacitor 12 is denoted as Q4; and a chargeheld in held in the first and the second capacitors 10 and 11 is denotedas Q5. A composite capacitance of the first and the second capacitors 10and 11 becomes 2C.

The circuit shown in FIG. 7 is one in which a negative feedback isachieved as in the circuit shown in FIG. 5, and the input terminal (−)is equivalently grounded.

Since the input terminal (−) of the operational amplifier 5 isequivalently grounded, a voltage held in the first capacitor 10 and thesecond capacitor 11 is outputted as an output voltage of the operationalamplifier 5. This output voltage is a result of the MDAC calculation.This output voltage Vout3 is obtained using Q5 as follows.

Vout3=Q5/2C   (10)

Next, according to the law of conservation of charge, the sum of Q3, Q4,and Q5 becomes equal to the charge Q which is firstly sampled.

Q=Q3+Q4+Q5   (11)

Using Equation (11), Q5 is expressed by the following equation.

Q5=Q−Q3−Q4   (12)

Next, a voltage to be applied to the fourth capacitor 13 becomesD1·Vref. Further, a voltage to be applied to the third capacitor 12becomes D2·Vref. Therefore, Q3 and Q4 are expressed by the followingequations.

Q3=4C·D1·Vref   (13)

Q4=2C·D2·Vref   (14)

Using Equations (2), (12), (13) and (14) above, Q5 becomes the followingvalue.

Q5=8C·Vin−4C·D1·Vref−2C·D2·Vref   (15)

Using Equations (10) and (15), Vout3 is given by the following equation.

Vout3=4Vin−2D1·Vref−d2·Vref   (16)

-   -   (D1,D2=−1 or 0 or 1)        This Vout3 is a second MDAC calculation result.

Next, the sub-A/D converter 6 performs a third A/D conversion accordingto the principle of the A/D conversion shown in FIG. 2 (Step S7). Thatis, Vout3 is converted into a third digital value in binary code so thatD3 is determined. Subsequently, the third digital value is sent to thedigital encoding circuit 15. Next, one selected from the switches 33 to35, one selected from the switches 28 to 30, and the switches 22, 27 areturned off.

Next, a third MDAC calculation is performed as follows (Step S8).

One of the switches 33 to 35 is selected according to a value of D1. Oneof the switches 28 to 30 is selected according to a value of D2. One ofthe switches 23 to 25 is selected according to a value of D3. At thistime, when D3=1, the switch 23 is selected; when D3=0, the switch 24 isselected; and when D3=−1, the switch 25 is selected.

Subsequently, one selected from the switches 33 to 35, one selected fromthe switches 28 to 30, one selected from the switches 23 to 25, and theswitch 22 are turned on. In this case, the circuit of FIG. 1 becomesequivalent to one shown in FIG. 8.

At this time, a charge held in the fourth capacitor 13 is denoted as Q6;a charge held in the third capacitor 12 is denoted as Q7; a charge heldin held in the second capacitor 11 is denoted as Q8; and a charge heldin held in the first capacitor 10 is denoted as Q9.

The circuit shown in FIG. 8 is the one in which a negative feedback isachieved as in the circuit shown in FIG. 5, and the input terminal (−)of the operational amplifier 5 is equivalently grounded.

Since the input terminal (−) of the operational amplifier 5 isequivalently grounded, a voltage held in the first capacitor 10 isoutputted as an output voltage of the operational amplifier 5. Thisoutput voltage is a result of the MDAC calculation. This output voltageVout4 is obtained using Q9 as follows.

Vout4=Q9/C   (17)

Next, according to the law of conservation of charge, the sum of Q6, Q7,Q8, and Q9 becomes equal to the charge Q which is firstly sampled.

Q=Q6+Q7+Q8+Q9   (18)

Using Equation (18), Q9 is expressed by the following equation.

Q9=Q−Q6−Q7−Q8   (19)

Next, a voltage to be applied to the fourth capacitor 13 becomesD1·Vref. Further, a voltage to be applied to the third capacitor 12becomes D2·Vref. Further, a voltage to be applied to the secondcapacitor 11 becomes D3·Vref. Therefore, Q6, Q7, and Q8 are expressed bythe following equations.

Q6=4C·D1·Vref   (20)

Q7=2C·D2·Vref   (21)

Q8=C·D3·Vref   (22)

Using Equations (2), (19), (20), (21), and (22) above, Q9 becomes thefollowing value.

Q9=8C·Vin−4C·D1·Vref−2C−D2·Vref−D3·Vref   (23)

Using Equations (17) and (23), Vout4 is given by the following equation.

Vout4=8Vin−4·D1·Vref−2C·D2Vref−D3·Vref   (24)

-   -   (D1,D2,D3=−1 or 0 or 1)        This Vout4 is a third MDAC calculation result.

Next, the sub-A/D converter 6 performs a fourth A/D conversion accordingto the principle of the A/D conversion shown in FIG. 2 (Step S9). Thatis, Vout4 is converted into a fourth digital value in binary code.Subsequently, the fourth digital value is sent to the digital encodingcircuit 15.

Next, the digital encoding circuit 15 adds the first to fourth digitalvalues according to the principle of digital encoding shown in FIG. 3,so that 5-bit digital encoding is performed. Subsequently, one selectedfrom the switches 33 to 35, one selected from the switches 28 to 30, oneselected from the switches 23 to 25, and the switch 22 are turned off.At this time, the A/D conversion operation is terminated.

As described above, since the sub-A/D converter having a redundancy isused in this embodiment, even in a state in which a residual signal isnot completely settled, when the sum of an error of the residual signaland an error of the sub-A/D converter is less than a predeterminedvalue, an accurate result using the A/D converter can be obtained.Therefore, the process is allowed to move to the next conversion stageimmediately after the time when an error of a residual signal attainswithin a predetermined value. Hence, the sub-A/D converter having aredundancy is allowed to move to the next conversion stage at an earlierpoint of time compared to a sub-A/D converter having no redundancy.

Further, the MDAC calculation is repeated using the charge sampledfirst. Therefore, it is not necessary to repeat sampling, and noise dueto the sampling is not accumulated.

That is, in this embodiment, since an accurate calculation due to aredundancy in calculation is not necessary, calculation cycle can beshortened, and an A/D converter with high noise tolerance can beconfigured. Further, since there is no delivery/receipt (sampling) of acharge, noise due to sampling is not accumulated.

Variation of this Embodiment

In this embodiment, an example of the A/D converter with 5 bit outputhas been presented, in which a conversion to a digital value is repeatedfour times using the sub-A/D converter 6. However, by changing acapacitance of a capacitor of the capacitor group 7 and the number ofcapacitors thereof, it is possible to configure an A/D converter, anoutput of which is not in 5 bits.

For example, in addition to the first capacitor 10 to the fourthcapacitor 13 of the capacitor group 7, when the capacitor group 7includes a capacitor of 8C eight times the capacitance of the firstcapacitor 10, the A/D converter becomes one having 6 bit output in whicha conversion to a digital value is repeated five times using the sub-A/Dconverter 6.

In the same manner, when m and n are positive integers not less than 2,and when the capacitor group 7 includes the first capacitor 10 to anm-th capacitor, an n-th capacitor has a capacitance of 2 ^((n−2))*C(n=2, 3, . . . , m) where C represents the capacitance of the firstcapacitor 10. In this case, the A/D converter becomes one having (m+1)bit output in which a conversion to a digital value is repeated m timesusing the sub-A/D converter 6.

Further, in this embodiment, capacitors have been used in each of whicha capacitance value is weighted according to a binary code being2^((n−2))*C. However, without being limited to the configuration methodof a capacitor switch group employed in this embodiment, various otherconfiguration methods are possible including, for example, one in whichall the capacitors are configured to have unit capacitance C.

Second Embodiment

An A/D converter of a second embodiment of the present invention will bedescribed. The second embodiment is an embodiment in which a pipelineA/D converter is configured in an application of the principle of thefirst embodiment of the present invention.

Configuration of Second Embodiment

FIG. 9 is a block diagram showing an A/D converter of the secondembodiment.

This embodiment has capacitor networks CN1 to CN5, switch networks SWN1to SWN5, a sampling unit SP, A/D converters AD1 to AD4, and a digitalencoding circuit 15. Incidentally, capacitor networks CN3 and CN4, andswitch networks SWN3 and SWN4 are not depicted in FIG. 9.

Capacitor network CN1 includes an external input terminal 1, referencevoltage selectors 2 to 4, a capacitor group 7, a first switch group 8,and a second switch group 9. Configurations and connections of theexternal input terminal 1, the capacitor group 7, the first switch group8, and the second switch group 9 are the same as those of the firstembodiment so that further descriptions thereof are omitted.

When an absolute value of a reference voltage in an A/D converter ofthis embodiment is denoted as Vref, as in the case of the firstembodiment, the reference voltage selectors 2 to 4 are circuits eachselecting one of voltages, i.e., a positive reference voltage +Vref, 0volt, and a negative reference voltage −Vref, in accordance with adigital value in binary code, having 1.5 bit of information, convertedby the sub-A/D converter 6 in A/D converters AD1 to AD4. In addition, asin the first embodiment, a digital value in binary code is supplied tothe digital encoding circuit 15.

The capacitor network CN1 stores an analog signal, inputted from theexternal input terminal 1, in the capacitor group 7 as a charge.Subsequently, after a digital value in binary code is supplied,predetermined voltages are selected by the reference voltage selectors 2to 4 in accordance with the digital value in binary code, and thecapacitor network CN1 transfers a charge stored in the capacitor group 7using the first switch group 8 and the second switch group 9.

Further, for capacitor network CN1, the number of times of converting ofvoltage is determined according to the number of switches in the firstswitch group 8 and the second switch group 9. In this embodiment, thisnumber of times is four.

The capacitor networks CN2 to CN5 have configurations each being thesame as that of capacitor network CN1.

The switch network SWN1 is a collection of switches, and includes aswitch group 1 and a switch group 2. The switch group SW1 connects oneends of the capacitor group 7 to the sampling unit SP, or to inputterminals (−) of operational amplifiers of A/D converters AD1 to AD4.The switch group SW2 connects one ends of the second switch group 9 ofcapacitor network CN1 to output terminals of the operational amplifiersof A/D converters AD1 to AD4.

The switch networks SWN2 to SWN5 each have two switch groups as in thecase of the switch network SWN1. That is, the switch network SWN2includes switch groups SW3 and 5W4; the switch network SWN3 includesswitch groups SW5 and SW6; the switch network SWN4 includes switchgroups SW7 and SW8; and the switch network SWN5 includes switch groupsSW9 and SW10.

Further, as in the function of the switch group SW1 to the capacitornetwork CN1, the switch groups SW3, SW5, SW7, and SW9 respectivelyconnect one ends of capacitor groups of the capacitor networks CN2 toCN5, to the sampling unit SP, or to input terminals (−) of theoperational amplifiers of A/D converters AD1 to AD4.

Further, as in the function of the switch group SW2 to the capacitornetwork CN1, the switch groups SW4, SW6, SW8, and SW10 respectivelyconnect one ends of the second switch group 9 of the capacitor networksCN2 to CN5, to output terminals of the operational amplifiers of A/Dconverters AD1 to AD4.

The above-described switch networks SWN1 to SWN5 connect the capacitornetworks CN1 to CN5, to the sampling unit SP and A/D converters AD1 toAD4 in one-to-one correspondence. That is, to one capacitor network, thesampling unit SP or one A/D converter is connected.

The sampling unit SP is grounded at one end thereof, and used whensampling analog signals inputted in capacitors of the capacitor networksCN1 to CN5. Incidentally, this grounding is to determine a referencepoint of a potential in a circuit, and, for example, the connection maybe made at 0 v.

An A/D converter AD1 includes a operational amplifier 5, and a sub-A/Dconverter 6. The operational amplifier 5 and the sub-A/D converter 6have the same functions as those of the first embodiment, so thatfurther descriptions thereof are omitted.

The A/D converter AD1 is a circuit which is connected to the capacitornetworks CN1 to CNn via the switch networks SWN1 to SWNn, and whichperforms an MDAC calculation, described in the first embodiment, basedon charges stored in the capacitor networks CN1 to CNn. Thus, an analogsignal is converted into a digital value. The converted digital value issupplied to the capacitor networks CN1 to CNn via the digital encodingcircuit 15.

The A/D converters AD2 to AD4 each also have the same configuration andfunction as those of the A/D converter AD1.

The digital encoding circuit 15 is the same circuit as that of the firstembodiment so that a further description there is omitted.

A/D Converter Operation of Second Embodiment

Next, A/D conversion operation used in this embodiment will be describedwith reference to FIGS. 10A and 10B.

FIG. 10A is a view showing an analog signal and an input state thereofin a capacitor network. FIG. 10B is a view showing a connection statebetween a capacitor network, and the sampling unit SP or A/D converters.That is, the view shows which one of the sampling unit SP and A/Dconverters AD1 to AD4 a capacitor network is connected at arbitrary timevia a switch network.

First, at time t1 shown in FIG. 10A, an analog signal at time t1 isinputted in the capacitor network CN1.

At this time t1, a connection state of the capacitor networks CN1 to CN5is as shown in FIG. 10B. That is, the capacitor network CN1 samples theinputted analog signal without being connected to the A/D converters.The capacitor network CN2 is connected to the A/D converter AD4 via aswitch network. Subsequently, switches in the capacitor network CN2 areswitched, so that the circuit configuration of FIG. 7 is changed to thatof FIG. 8, and that a third MDAC calculation and a fourth A/D conversionare performed. The capacitor network CN3 is connected to the A/Dconverter AD3 via a switch network. Subsequently, switches in thecapacitor network CN3 are switched, so that the circuit configuration ofFIG. 6 is changed to that of FIG. 7, and that a second MDAC calculationand a third A/D conversion are performed. The capacitor network CN4 isconnected to the A/D converter AD2 via a switch network. Subsequently,switches in the capacitor network CN4 are switched, so that the circuitconfiguration of FIG. 5 is changed to that of FIG. 6, and that a firstMDAC calculation and a second A/D conversion are performed. Thecapacitor network CN5 is connected to the A/D converter AD1 via a switchnetwork, and the circuit becomes the circuit configuration of FIG. 5, sothat a first A/D conversion is performed.

Next, at time t2, the capacitor network CN1 is connected to the A/Dconverter AD1; the capacitor network CN2 is connected to the samplingunit SP; the capacitor network CN3 is connected to the A/D converterAD4; the capacitor network CN4 is connected to the A/D converter AD3;and the capacitor network CN5 is connected to the A/D converter AD2.

Incidentally, in this embodiment, sampling time is represented by ts asshown in FIG. 10A.

In the same manner, a capacitor network into which the analog signal isinputted is changed with time from the capacitor network CN1 to thecapacitor network CN5. A subject to which each capacitor network isconnected is changed from the sampling unit SP to the A/D converter AD1to the A/D converter AD4. These series of connecting operations arerepeated.

When being connected to the sampling unit SP, each capacitor networkperforms sampling on an analog signal. When being connected to the A/Dconverter AD1, the circuit configuration becomes one shown in FIG. 5,and a first A/D conversion is performed. When being connected to the A/Dconverter AD2, the circuit configuration of FIG. 5 becomes that of FIG.6, and a first MDAC calculation and a second A/D conversion areperformed. When being connected to the A/D converter AD3, the circuitconfiguration of FIG. 6 becomes that of FIG. 7, and a second MDACcalculation and a third A/D conversion are performed. When beingconnected to A/D converter AD4, the circuit configuration of FIG. 7becomes that of FIG. 8, and a third MDAC calculation and a fourth A/Dconversion are performed.

As described above, in this embodiment, by switching connections betweencapacitor networks, and the sampling unit SP or a plurality of A/Dconverters, an A/D conversion in pipeline operation is achieved.Accordingly, a sampling time interval becomes small compared with thefirst embodiment, so that a conversion rate of A/D conversion can beincreased.

Variation of Second Embodiment

In this embodiment, an example of the A/D converter with 5 bit outputhas been presented, in which a conversion to a digital value is repeatedfour times using an A/D converter. However, as in the first embodiment,the capacitance of a capacitor of the capacitor group 7, the number ofcapacitors thereof, and the number of A/D converters may be changed sothat this embodiment can be applied to an A/D converter, an output ofwhich is not in 5 bits.

In this embodiment, five capacitor networks have been used, but anyother number of capacitor networks can be used. At this time, the numberof sampling units is one, and sampling units and A/D converters areconfigured so that the sum of the numbers of sampling units and A/Dconverters is equal to the number of capacitor networks.

Other Embodiments

By changing a redundancy of a sub-A/D converter, the first and secondembodiments can be also applied to an A/D converter with a redundancybeing other than 5 bits, for example, 2.5 bits or 3.5 bits.

When the redundancy is 2.5 bits, a redundancy of 1 bit is added to abinary code of 2 bits so that the binary code becomes 3 bits in total.When performing digital encoding, a sub-A/D converter overlaps an LSB ofa digital value in 3 bits which is converted at an n-th time, and an MSBof a digital value in 3 bits which is converted at an n+1-th time.

In the same way, when the redundancy is an arbitrary n.5 bits, aredundancy of 1 bit is added to a binary code of n bits so that thebinary code becomes n+1 bits in total. When performing digital encoding,a sub-A/D converter overlaps an LSB of a digital value in n+1 bits,which is converted at an m-th time, and an MSB of a digital value in n+1bits, which is converted at an m+1-th time.

Further, the first and second embodiments each can be configured to beone in which a conventional cyclic A/D converter and a conventional A/Dconverter are combined so as to be, for example, used for a specificcalculation in an upper bit or a lower bit.

Still further, the circuit configurations of the first and secondembodiments can be applied to those of differential circuits.

As described above, although the present invention has been describedusing the above-described embodiments, it is to be understood that thepresent invention is not limited to the embodiments, and various changesmay be made therein without departing from the spirit of the presentinvention. Such changes are also included in the scope of the presentinvention.

1. An analog-to-digital converter comprising: a first switch groupconfigured to be connected to an input terminal, and an analog signalbeing inputted into the input terminal; a capacitor group configured tobe connected to the first switch group, and the capacitor group stores,as a charge, the analog signal inputted from the input terminal; asecond switch group configured to being connected to the capacitorgroup, and the second switch group transfers the charge in the capacitorgroup; a operational amplifier configured to be connected to thecapacitor group and the second switch group, the operational amplifiersubtracts a predetermined voltage from a voltage generated in thecapacitor group in conjunction with the transfer of the charge, and theoperational amplifier then sets, as an output voltage, a voltageobtained by amplifying the result of the subtraction; converterconfigured to be connected to the operational amplifier, and theconverter converts the output voltage into a digital value of apredetermined number of bits including a redundancy bit; and a pluralityof reference voltage selectors configured to be connected to the firstswitch group and the capacitor group, and each of the plurality ofreference voltage selectors selects the predetermined voltage inaccordance with the digital value, wherein the connecting of thecapacitor group to the operational amplifier, and the voltage selectionof each reference voltage selector, are performed for a plurality oftimes.
 2. The analog-to-digital converter according to claim 1, thedigital value of a predetermined number of bits is a digital value inbinary code in accordance with the output voltage.
 3. Theanalog-to-digital converter according to claim 1, in the converter, MDACcalculation operation is held in accordance with the output voltage. 4.The analog-to-digital converter according to claim 1, the predeterminedvoltage is one of the following voltage, a positive reference voltage+Vref, 0 volt, and a negative reference voltage −Vref.
 5. Theanalog-to-digital converter according to claim 1, further comprising adigital encoding circuit configured to add a plurality of the digitalvalues together, and the digital encoding circuit configured to performan error correction.
 6. The analog-to-digital converter according toclaim 5, the error correction is that the digital values are overlapedand added.